Solid state power amplifiers are advantageous for their compact size and easy integration into semiconductor circuit components. Unfortunately, the methods of manufacture for present day semiconductor power amplifiers require a semiconductor substrate dedicated to power amplifier devices or many processing steps in addition to common semiconductor processing steps for typical semiconductor complementary metal-oxide-semiconductor (CMOS) devices or their variants.
For example, high-end power amplifiers are built in gallium arsenide (GaAs) technologies, which require a GaAs substrate and dedicated processing steps that are not compatible with silicon-based CMOS technologies. As a result, the power amplifiers that utilize GaAs technologies tend to be costly. Middle-range power amplifiers are built in modified silicon germanium bipolar complementary metal-oxide-semiconductor (SiGe BiCMOS) technologies developed for high voltage power applications. Even modified SiGe BiCMOS technologies tend to add its own cost associated with enabling power amplifiers. Enabling power amplifiers in standard CMOS technologies also tends to introduce many new processing steps and device modifications to accommodate the high voltages that the power amplifiers require, thus also increasing the manufacturing cost for the power amplifiers.
A junction field effect transistor (JFET) is a semiconductor device in which the current between a source and a drain is controlled by the voltage applied to a junction gate terminal, or a “gate.” Unlike a metal-oxide-semiconductor field effect transistor (MOSFET), the gate of a JFET is not insulated from the source and the drain. Instead, the body of the transistor and the gate of the transistor form a reverse-biased pn junction with depletion regions both in the gate and in the body. Therefore, the JFET is a depletion mode device with a high input impedance. The input signal is supplied to the gate, typically in the form of a voltage input. The output is the current between the source and the drain which is modulated by the input voltage at the gate.
A typical JFET comprises a source and a drain that are heavily doped with dopants of a first conductivity type, i.e., p-type or n-type, at a peak dopant concentration typically in the range from about 1.0×1020/cm3 to about 3.0×1021/cm3. The body of the JEFT is also doped with dopants of the first conductivity type at a dopant concentration typically in the range from about 1.0×1017/cm3 to about 1.0×1019/cm3. A channel is formed within the body along the pn junction boundary. The gate, located on the body and separated from the source and the drain, is heavily doped with dopants of a second conductivity type, which is the opposite type of the first conductivity type, at a peak dopant concentration typically in the range from about 1.0×1020/cm3 to about 3.0×1021/cm3. A voltage bias is applied between a gate contact and a body contact to forms a reverse biased pn junction between the gate and the body. The gate contact and the body contact directly contact the gate and the body, respectively, and are typically a metal semiconductor alloy.
On a circuit level, the JFET gate presents a small current load, which is the reverse bias leakage of the gate-to-channel junction. The current load of a JFET, i.e., the gate current, is higher than the current load of a typical MOSFET, since the MOSFET has an extremely low gate current, for example, in the range of picoamperes, due to an insulator between the gate and the channel, i.e., a gate dielectric. However, the gate current of a typical JFET is much lower compared to the base current of a typical bipolar junction transistor (BJT), and the transconductance of a typical JFET is higher than that of a typical MOSFET, enabling handling of a higher current. For this reason, JFETs are used in high-input impedance linear amplifier circuits. Use of JFETs as a switch in power semiconductor circuits is also known.
While the power amplification properties of JFETs are desirable, integration of prior art JFETs into standard CMOS process integration scheme, however, adds many processing steps in a manner similar to other attempts to incorporate power amplifiers into standard semiconductor technologies.
Therefore, there exists a need for a semiconductor structure that provides power amplification, is compatible with standard CMOS technology, and requires a minimal number of additional processing steps, and methods of manufacturing the same.
Specifically, there exists a need for a JFET structure that is compatible with standard CMOS technology and methods of manufacturing the same with a minimal incremental processing cost.